Current methods for manufacturing a three-dimensional thin-film solar cell (3-D TFSC) include forming a 3-Dimensional thin-film silicon substrate (3-D TFSS) using a silicon template. The template may comprise a plurality of posts and a plurality of trenches between said a plurality of posts. The 3-D TFSS may then be formed by forming a sacrificial layer on the template, subsequently depositing a semiconductor layer, selective etching the sacrificial layer and releasing the semiconductor layer from the template. More specifically, the semiconductor layer is a self-supporting, free-standing three-dimensional (3D) epitaxial silicon thin film deposited on and released from a low-cost reusable crystalline silicon substrate template. The reusable silicon template may be reused to form the 3D film numerous times before being reconditioned or recycled. Select portions of the released 3-D TFSS are then doped with a first dopant, and other select portions are than doped with a second dopant. After surface passivation processes, emitter and base metallization regions are formed to complete the solar cell structure. FIG. 1A illustrates a partial view of a re-usable mono-crystalline silicon template with hexagonal-prism posts according to the U.S. Patent Pub. No. 2008/0264477A1 by common inventor Mehrdad M. Moslehi and which is hereby incorporated by reference. FIG. 1B illustrates a partial view of a 3D thin-film, hexagonal-honeycomb-prism substrate with rear/bottom base silicon layer after release from the reusable template according to the U.S. Patent Pub. No. 2008/0264477A1.
The above referenced three-dimensional thin film solar cell templates, substrates, and cells provide cost, performance, and mechanical strength advantages compared to traditional flat solar cells with a similar amount of silicon because 3-D TFSC have superior mechanical strength, better light trapping, and lower cell processing costs because of their self-aligned nature.
From a mechanical structure perspective, given a fixed amount of silicon structural material, a honeycomb 3-D TFSS may provide a desirable mechanical rigidity and strength. However, from the fabrication process perspective, the trenches among the neighboring hexagonal pillars on the template need to be filled by epitaxial silicon growth and the substrate formed by the filled layer needs to be released from the template. These processes are often costly and difficult. Design and process improvements need to be made in making the relatively high aspect ratios trenches, epitaxial filling of the trenches and releasing a TFSS from the trenches.
Additionally, known flat thin film solar cells often require surface texturing to reduce reflectance losses which requires a minimum film thickness of preferably tens of microns (e.g., >30 μm) to avoid texturing etch-induced punch-through pinholes. Also, flat thin-film silicon substrates may have reduced mean optical path length which reduces IR absorption and results in reduced cell quantum efficiency. And flat thin-film crystalline silicon substrates may have poor mechanical strength for cell and module processing needs. Micro cracking defects at substrate edges and pinholes defects within the substrate could cause cracking initiations and these cracks propagate easily along the crystallographic directions.
Mono-crystalline silicon is the most extensively used material for photovoltaic applications and efficiencies up to 24% have been achieved using lab-cell processes. But the high cost of high-quality silicon material limits the widespread use of such solar modules. Layer transfer processes with the aim to form a thin mono-crystalline silicon film separated/cleaved from a silicon wafer have been developed. U.S. Patent Publication No. US2009/0042369A1 describes such a method for fabricating a free-standing flat or co-planar silicon layer by using high energy implantation and associated thermal treatment and cleaving processes. Similar methods have been developed and used for making SOI wafers—such as process disclosed in U.S. Pat. No. 5,374,564.
There are a number of major issues, problems, and challenges with the use of flat or co-planar silicon thin films (e.g., films with thicknesses of well below 50 μm) for high-performance solar cells, including but not limited to:
(1) Difficulties associated with sufficient surface texturing of the thin silicon film to reduce surface reflectance losses. For example, planar (111) orientation silicon wafers are used in the layer transferring method disclosed in U.S. Patent Pub. No. 2009/0042369A1 for the ease of cleaving along the (111) directions. However it is difficult and costly to create surface texturing on flat surfaces that are made of (111) crystal planes.
(2) Substantially reduced mean optical path length resulting in reduced photon absorption, particularly for photons with energies near the infrared bandgap of silicon, resulting in reduced solar cell quantum efficiency (reduced short-circuit current density or Jsc).
(3) Lack of rigidity and mechanical support of the thin film during cell and module processing steps. This disadvantage relates to the mechanical strength of a large-area (e.g., 200 mm×200 mm) thin silicon film. It is well known that reducing the large-area crystalline silicon wafer thickness to below 100 μm results in a substantial loss of mechanical strength/rigidity and such thin wafers tend to be flexible and very difficult to handle without breakage through the entire cell fabrication process flow. As a result, large-area, co-planar (flat) silicon films thinner than, for instance, 50 μm must be properly mounted and supported on a cost-effective substrate for high-yield solar cell and module processing.